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? 2010 semtech corporation power management 1 SC122 low voltage synchronous boost converter features input voltage 0.7v to 1.6v minimum start-up voltage 0.85v output voltage xed at 3.3v peak input current limit 350ma typically output current 95ma at v in = 1.6v, 50ma at v in = 0.9v e ciency up to 80% internal synchronous recti er switching frequency 1.2mhz power save (voltage hysteretic) control anti-ringing circuit operating supply current (measured at out) 40a no forward conduction path during shutdown mlpd-ut-6 1.5 2.0 0.6 (mm) package lead-free and halogen-free weee and rohs compliant applications electric toothbrushes personal medical products single-cell alkaline, nicd, or nimh applications ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC122 is a high efficiency, low noise, synchronous step-up dc-dc converter. it produces a xed 3.3v output from a single cell alkaline or nimh battery. it features an internal 1.2a switch and synchronous recti er to achieve high e ciency and to eliminate the need for an external schottky diode. the SC122 operates exclusively in voltage-hysteretic power save mode (psave) for high e ciency under light load conditions. it features anti-ringing circuitry for reduced emi in noise sensitive applications. while dis- abled, the output remains in a high impedance state to preserve the charge on the output capacitor. this permits ultra-low idle quiescent currents in applications in which the SC122 can be periodically enabled by an external con- troller to recharge the output capacitor. low quiescent current is obtained despite a high 1.2mhz operating frequency. small external components and the space saving mlpd-ut-6, 1.52.00.6 (mm) package, make this device an excellent choice for small handheld applications that require the longest possible battery life. l1 c in 3.3v single cell (1.2v) in out lx en gnd SC122 c out gnd typical application circuit february 1, 2010
SC122 2 pin con guration marking information ordering information device package SC122ultrt (1)(2) mlpd-ut-6 1.52 SC122evb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) lead-free packaging only. device is weee and compliant and halogen-free. top view t in en gnd gnd out lx 6 5 4 1 2 3 mlpd-ut; 1.5 2, 6 lead ja = 84c/w 122 yw mlpd-ut; 1.52, 6 lead yw = date code
SC122 3 exceeding the above speci cations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. absolute maximum ratings in, out, lx (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 en (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v in + 0.3) esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 recommended operating conditions ambient temperature range (c) . . . . . . . . . . . . . . 0 to +70 v in (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 to 1.6 v out (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 thermal information thermal resistance junction-ambient (2) (c/w) . . . . . . . 84 maximum junction temperature (c) . . . . . . . . . . . . . . . 150 storage temperature range (c) . . . . . . . . . . . -65 to +150 peak ir re ow temperature (10s to 30s) (c) . . . . . . +260 unless otherwise noted v in = 1.2v, c in = c out = 22f, l 1 = 4.7h, t a = 0 to +70c. typical values are at t a = 25c. parameter symbol conditions min typ max units input voltage range v in 0.7 1.6 v output voltage v out 3.3 v output accuracy v out-tol v en = v in -3 3 % minimum startup voltage v in-su i out < 1ma 0.85 v operating supply current (1) i out-q v en = v in , i out = 0ma, v out = 3.3v 40 a disabled out leakage current i out-dis v en = 0, v out = 3.3v (externally forced) 2 a disabled in quiescent current i in-dis v en = 0, v in = 1.6, v out = 3.3v (externally forced) 4 a shutdown current i in-shdn v en = 0v, v in = 1.6v, v out = 0v 8.5 a internal oscillator frequency f osc while bursting 1.2 mhz startup time t su from v en low-to-high transition 1 ms minimum v in for restart (2) v in-restart lowest v in to ensure re-enable within 300s, v out = 3.1v (externally forced) 1.0 v p-channel on resistance r ds(on)p i lx = 50ma 0.6 n-channel on resistance r ds(on)n i lx = 50ma, v in =1.6v 0.5 p-channel startup current limit i lim(p)-su v in = 1.2v, v en > v ih 100 ma electrical characteristics
SC122 4 parameter symbol conditions min typ max units n-channel current limit i lim(n) v in = 1.2v 350 ma lx leakage current pmos i lxplk t a = 25c, v lx = 0v, v out = 3.3v 1 a lx leakage current nmos i lxnlk t a = 25c, v lx = 3.3v, v out = 3.3v 1 a logic input high v ih v in = 1.2v 0.4 v logic input low v il v in = 1.2v 0.1 v logic input current high i ih v en = v in = 1.2v 1 a logic input current low i il v en = 0v -0.2 a electrical characteristics (continued) notes: (1) quiescent operating current is drawn from the out pin while in regulation. the quiescent operating current projected to t he in pin is approximately i q (v out /v in ). (2) restart occurs when the en pin transitions from low to high while the output voltage is at or near the regulation value (3 .3v). see the application section the enable pin for details.
SC122 5 typical characteristics v out = 3.3v e ciency vs. i out 0.1 0.2 0.5 1 2 5 10 20 50 100 0 10 20 30 40 50 60 70 80 90 100 i out (ma) efficiency (%) l = 4.7 h, v in = 1.2v e ciency vs. i out 0.1 0.2 0.5 1 2 5 10 20 50 100 0 10 20 30 40 50 60 70 80 90 100 i out (ma) efficiency (%) l = 4.7 h, t a = 25 c v in = 1.2v v in = 0.9v v in = 1.6v t a = 25c t a = 70c t a = 0c load regulation 0 10 20 30 40 50 60 70 80 90 100 3.25 3.26 3.27 3.28 3.29 3.3 3.31 i out (ma) v out (v) l = 4.7 h, v in = 1.2v load regulation 0 10 20 30 40 50 60 70 80 90 100 3.25 3.26 3.27 3.28 3.29 3.3 3.31 i out (ma) v out (v) l = 4.7 h, t a = 25 c v in = 1.2v v in = 1.6v v in = 0.9v t a = 25c t a = 0c t a = 70c line regulation high load 0.7 1 1.3 1.6 3.25 3.26 3.27 3.28 3.29 3.3 3.31 v in (v) v out (v) l = 4.7 h, i out = 45ma line regulation low load 0.7 1 1.3 1.6 3.25 3.26 3.27 3.28 3.29 3.3 3.31 v in (v) v out (v) l = 4.7 h, i out = 1ma t a = 0c, 25c, 70c t a = 0c, 25c, 70c
SC122 6 0.7 1 1.3 1.6 0 20 40 60 80 100 120 140 160 v in (v) equivalent r load ( ) l = 4.7 h 0.7 1 1.3 1.6 0 10 20 30 40 50 v in (v) i out (ma) l = 4.7 h typical characteristics v out = 3.3v (continued) 0 10 20 30 40 50 60 70 3.25 3.26 3.27 3.28 3.29 3.3 3.31 junction temperature ( o c) v out (v) l = 4.7 h, i out = 45ma 0 10 20 30 40 50 60 70 3.25 3.26 3.27 3.28 3.29 3.3 3.31 junction temperature ( o c) v out (v) l = 4.7 h, i out = 1ma v in = 1.2v v in = 1.6v v in = 0.9v v in = 1.2v v in = 1.6v v in = 0.9v t a = 25c t a = 70c t a = 0c t a = 25c t a = 70c t a = 0c 0.7 1 1.3 1.6 0 20 40 60 80 100 120 v in (v) i out (ma) l = 4.7 h v out = 3.3v, i out = 1ma temperature (c) startup voltage (v) 0.6 0.65 0.7 0.75 0.8 0.85 0.9 010203040506070 temperature regulation high load temperature regulation low load startup min. load resistance vs. v in startup max. load current vs. v in maximum i out vs. v in minimum start-up voltage vs. temperature t a = 25c t a = 70c t a = 0c
SC122 7 pin descriptions mlpd pin # pin name pin function 1 lx switching node connect an inductor from the input supply to this pin. 2, 5 gnd signal and power ground connections. 3 in battery input and damping switch connection. 4 en enable digital control input active high. 6 out output voltage supply pin requires an external 10f bypass capacitance (e ective under v out bias) for normal operation. t thermal pad thermal pad is for heat sinking purposes connect to ground using multiple vias, not connected internally.
SC122 8 block diagram - + v ref 1.2 v start-up oscillator gate drive and logic control error amp. oscillator - + - + - + + - p lim amp. 1.7 v v out comp. 1 6 5 2 4 3 in en gnd gnd lx out bulk bias + - n lim amplifier
SC122 9 detailed description the SC122 is a synchronous step-up hysteretic dc-dc converter utilizing a 1.2mhz xed frequency switching architecture. it provides a xed 3.3v output from an input voltage as low as 0.7v, with an unloaded startup input voltage of 0.85v. the SC122 operates exclusively in psave regulation mode (bursts of switching boost cycles, alternating with periods of an output-high-impedance state). it has quiescent current consumption as little as 40a into the out pin. it features anti-ringing circuitry for reduced emi in noise sensitive applications. the boost cycles can be disabled with an active-high enable input. while disabled, the output remains in a high impedance state to preserve the charge on the output capacitor. this permits ultra-low idle quiescent currents in applications in which the SC122 can be periodically enabled by an external controller to recharge the output capacitor. the regulator control circuitry is shown in the block diagram. it is comprised of a feedback controller, an inter- nal 1.2mhz oscillator, an n-channel field e ect transistor (fet) between the lx and gnd pins, and a p-channel fet between the lx and out pins. the current owing through both fets is monitored and limited as required for startup and psave regulator operation. an external inductor must be connected between the in pin and the lx pin. during the burst phase of psave operation, the controller alternates between the on-state and the o -state. during the on-state the n-channel fet is turned on, grounding the inductor at the lx pin. this causes the current owing from the input supply through the inductor to ground to ramp up. the on-state continues until the rst of two limits is reached, either the n-channel current limit i lim(n) , or the on- time limit t on-max = 0.9 1/f osc . then during the o -state, the n-channel fet is turned o and the p-channel fet is turned on, connecting the inductor between in and out. the (now decreasing) inductor current ows from the input to the output, transferring the inductor energy to the output and boosting the output voltage above the input voltage for the remainder of the cycle period t = 1/f osc . the cycle then repeats to re-energize the inductor. the burst phase continues until v out reaches an upper voltage threshold, at which point both fets are turned o . this begins the high-impedance phase. the output capacitor then discharges into the load until v out reaches a lower voltage threshold, which initiates a new burst phase. the upper and lower voltage thresholds di er by approximately 50mv, and were chosen to provide an average output voltage of 3.3v. the time between bursts is determined by the discharge rate of the output capaci- tor, which depends on the value of output capacitance and the magnitude of the applied load. figure 1 illus- trates psave regulation. time = (10s/div) v in = 1.5v, i out = 20ma v out ripple (50mv/div) i l (100ma/div) v lx (5v/div) figure 1 psave regulation waveforms the enable pin the en pin is a high impedance logical input that can be used to enable or disable the SC122 under processor control. v en > 0.4v will enable the output. the startup sequence from the en pin is identical to the startup sequence from the application of input power. v en < 0.1v will disable regulation and set the lx pin in a high-impedance state (turn o both fet switches). the out pin is also left in a high-impedance state when dis- abled. the SC122 can be disabled while maintaining the output voltage on the output capacitor, for the lowest possible quiescent current, while supporting a low appli- cation idle state load. the SC122 can then be periodically re-enabled for a brief time to refresh the charge held on the output capacitor, then disabled for an extended time as determined by the discharge rate of the output capaci- tor while supplying the idle-state load current. for v in > v in-restart , and over the full specified temperature range, regulation will be fully enabled within 300s of a high voltage on the en pin with v out discharged to as low as 2.5v. applications information
SC122 10 applications information (continued) a suggested very low duty cycle refresh oscillator circuit is included on the SC122 evb-rm, the SC122 evaluation board with refresh modulation. regulator startup, short circuit protection, and current limits the SC122 permits power up at input voltages from 0.85v to 1.6v. startup current limiting of the internal switching n-channel and p-channel fet power devices protects them from damage in the event of a short between out and gnd. this protection prevents startup into an exces- sive load. at the beginning of the cycle, the p-channel fet between the lx and out pins turns on with its current limited to approximately 100ma, the short-circuit output current. when v out approaches v in (still below 1.7v), the n-channel current limit is set to 350ma (the p-channel limit is dis- abled), an internal oscillator turns on (approximately 200khz), and a xed 75% duty cycle pwm-type operation begins. when the output voltage exceeds 1.7v, xed fre- quency psave operation begins, with the duty cycle deter- mined by an n-channel fet peak current limit of 350ma. note that startup with a regulated active load is not the same as startup with a resistive load. the resistive load output current increases proportionately as the output voltage rises until it reaches v out /r load , while a regulated active load presents a constant load as the output voltage rises from 0v to v out . note also that if the load applied to the output exceeds the startup current limit, the criterion to advance to the next startup stage may not be achieved. in this situation startup may pause at a reduced output voltage until the load is reduced further. output overload and recovery as the output load increases, the duration of each burst increases, and the time between bursts decreases. the output load reaches its maximum when the burst dura- tion becomes inde nite (and the time between bursts becomes zero). at this time, all the energy stored in the inductor during the on-time portion of each burst cycle is discharged into the output during o -time. the inductor current reduces to zero just as the next on-time begins. above this critical maximum load, the output voltage will decrease rapidly, and the startup current and switching limits will be invoked in reverse order as the output voltage falls through its various startup voltage thresh- olds. how far the output voltage drops depends on the load voltage vs. current characteristic. a reduction in input voltage, such as a discharging battery, will lower the load current at which overload occurs. at the overload threshold, the energy stored in the inductor at the end of each on-time is the same for all v in . but since the voltage increase above the input voltage is greater, the available output current, i out = p/(v out - v in ), must decrease. when an overload has occurred, the load must be decreased to permit recovery. the conditions required for overload recovery are identical to those required for successful initial startup. anti-ringing circuitry when both fet switches are simultaneously turned o , an internal switch between the in and lx pins is closed. this provides a moderate resistance path across the inductor to dampen the oscillations at the lx pin. this e ectively reduces emi that can develop from the reso- nant circuit formed by the inductor and the drain capaci- tance at lx. the anti-ringing circuitry is disabled between psave bursts. inductor selection the inductance value primarily a ects the amplitude of inductor current ripple ( i l ). the inductor peak current i l-max = i l-avg + i l /2, where i l-avg is the inductor current aver- aged over a full on/o cycle, is subject to the n-channel fet peak current limit i lim(n) . the inductor average current is equal to the output load current. increasing inductance reduces i l and therefore increases the maximum sup- portable output current. the performance plots of this datasheet were obtained with l = 4.7h. larger values of inductance can provide higher maximum output currents. any chosen inductor should have low dcr, compared to the r ds-on of the fet switches, to maintain e ciency. for dcr << r ds-on , further reduction in dcr will provide diminishing bene t. the inductor i sat value must exceed i lim(n) . the inductor self-resonant frequency should exceed
SC122 11 5f osc . any inductor with these properties should provide satisfactory performance. the following table lists the manufacturers of recom- mended inductor options. manufacturer/ part # value (h) dcr (m) rated current (ma) tolerance (%) dimensions lwh (mm) sumida 5508472xxxx 4.7 3800 90 2/5/10/20 2.2 1.4 1.6 murata lqm31pn4r7m00l 4.7 300 700 20 3.2 1.6 0.85 capacitor selection low esr capacitors such as x5r or x7r type ceramic capacitors are recommended for input bypassing and output ltering. low-esr tantalum capacitors are not rec- ommended due to possible reduction in capacitance seen at the switching frequency of the SC122. ceramic capaci- tors of type y5v are not recommended as their tempera- ture coefficients make them unsuitable for this application. the input and output each require a minimum capaci- tance value of 10f at the programmed output voltage. this must be considered when choosing small package size capacitors as the dc bias must be included in their derating to ensure this required value. for example, a 10f 0805 capacitor may provide su cient capacitance at low output voltages but may be too low at higher output voltages. therefore, a higher nominal capacitance value may be required to provide the minimum of 10f at these higher output voltages. additional output capacitance can be used extend the time between bursts, or to improve load transient response. the following table lists recom- mended capacitors. manufacturer/ part number value (f) rated voltage (vdc) type case size murata grm21br60j226me39b 22 6.3 x5r 0805 murata grm31cr71a226ke15l 22 10 x7r 1206 pcb layout considerations good layout can enhance the performance of the dc-dc converter and can avoid emi problems, ground bounce, and resistive voltage losses. the recommended layout is shown in figure 2. the following simple design rules can be implemented to ensure good layout: place the inductor and lter capacitors as close to the device as possible and use short wide traces between the power components. maximize ground metal on the component side to improve the return connection and thermal dissipation. separation between the lx node and gnd should be maintained to avoid cou- pling capacitance between the lx node and the ground plane. use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. ? ? ? applications information (continued) v out gnd c in c out SC122 gnd en in lx l x out gnd 6.7mm 5.2mm figure 2 recommended layout
SC122 12 (laser mark) indicator pin 1 1 n 2 min aaa bbb b e l n d a1 a dim millimeters nom dimensions max nom inches min max a a1 d1 e1 .035 .035 .026 .031 0.80 0.65 0.90 0.90 .055 -- 1.40 e .079 2.00 - - bxn a2 (.006) (.152) .055 .063 1.40 1.60 .075 .083 1.90 2.10 a2 lxn d e e1 d1 notes: controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as terminals. 2. 1. .003 .007 6 .010 .059 .000 .020 0.08 0.25 6 .012 0.18 .024 .002 0.00 0.50 0.30 1.50 0.05 0.60 .004 0.10 0.50 bsc .020 bsc 0.30 .012 .016 .014 0.35 0.40 aaa c seating plane a bbb c a b b e c - - outline drawing mlpd-ut-6 1.5x2
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information SC122 13 land pattern mlpd-ut-6 1.5x2 k h .031 .051 0.80 1.30 .106 .020 .012 .030 2.70 0.30 0.75 0.50 (.077) .047 1.20 (1.95) notes: 2. thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane. functional performance of the device. failure to do so may compromise the thermal and/or inches dimensions g k h x y p z c dim millimeters (c) g z p x r .006 0.15 r 3. y 1. controlling dimensions are in millimeters (angles in degrees). this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met.

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